1. Field of the Invention
The invention relates to an output stage structure, and more particularly, to a complementary MOS transistor output structure with high voltage tolerance.
2. Description of the Prior Art
As technology develops, the design of metal oxide semiconductor (MOS) transistor has also been moving toward the direction of smaller size, higher speed, lower power consumption, and lower supply voltage. Along with the development of a core circuit, a lower supply voltage is also utilized for increasing the circuit reliability. For instance, 0.5 um technology is utilized with 5V supply voltage for fabricating a core circuit whereas 0.25 um technology is utilized with 0.25V supply voltage for fabricating a core circuit. Nevertheless, the supply voltage of interface or peripheral circuits, due to the specification requirement, is often not decreased along with core circuit. For example, a transistor-transistor logic (TTL) interface of a digital circuit may require a 3.3V input/output voltage, a class D amplifier of a analog circuit may require a 12V MOS switch voltage, and a line driver may often require a 12V supply voltage for achieving the power transmission etc.
Traditionally, high voltage circuits often require high voltage tolerance devices that are capable of carrying out normal operations under high voltage conditions as well as maintaining a relatively long lifetime. Nevertheless, the fabrication of these high voltage tolerance devices often requires an additional high voltage fabrication process and also brings a disadvantage to the integration of interface circuit and core circuit. In recent years, numerous methods without utilizing high voltage tolerance devices for output stage applications have been widely discussed, such as the “5.5-V I/O in a 2.5-V 0.25-um CMOS Technology” disclosed in “IEEE Journal of Solid-State Circuits, vol. 36, no. 3, March 2001”, or “A High-Voltage Output Driver in a Standard 2.5V 0.25 um CMOS Technology” disclosed in “2004 IEEE International Solid-State Circuit Conference, Session 7, TD: Scaling Trends, 7.8”, and “Designing Outside Rail Constraints” disclosed in “2004 IEEE International Solid-State Circuit Conference, Session 7, TD: Scaling Trends, 7.2”.
Please refer to FIG. 1. FIG. 1 is a perspective diagram showing the high voltage tolerance output stage according to the prior art, which can be applied to digital output or analog signals. As shown in FIG. 1, a plurality of MOS transistors 102, 104 use cascode connection for lowering the voltage difference. In other words, the voltage across any two points of all the MOS transistors 102, 104 is controlled to be less than the supply voltage (VDD, nom) of normal core circuit by utilizing an appropriate bias circuit 106. In general, the core circuit fabricated by 0.25 μm technology under 2.5V supply voltage (VDD, nom) is capable of tolerating 5V voltage at output stage.
Please refer to FIG. 2. FIG. 2 is a cross-section diagram showing the structure of the high voltage tolerance output stage according to the prior art, in which the structure is a cascode complementary MOS transistor. As shown in FIG. 2, an n well 302 is formed within a p substrate 304, in which a plurality of p+ dopants 306 is formed on top of the n well 302 for forming the source and drain of the PMOS transistor and a plurality of n+ dopants 308 is formed on top of the p substrate 304 for forming the source and drain of the NMOS transistor. The source and drain situated in proximity to the PMOS or NMOS itself transistors are coupled with each other, and the source and drain in between the PMOS and NMOS transistors are not only coupled with each other, but are also coupled to an output pad 314. The gate 318 of the PMOS transistor and the gate 320 of the NMOS transistor are coupled to a bias circuit 316 for controlling the output stage. Hence the voltage across any two points will be controlled to be less than the supply voltage (VDD, nom) of a normal core circuit under any circumstances.
Since all PMOS transistors from the high voltage tolerance output stage structure shown in FIG. 2 utilize the same n well 302 and all NMOS transistors utilize the same p substrate 304, it is unattainable to control the body bias voltage of each NMOS or PMOS individually. The condition will become worse when the supply voltage (VDD) of output stage (such as under the condition of a line driver at 12V) increases, and as the voltage of the output pad 314 exceeds a certain voltage limitation, a junction breakdown or junction leakage will occur on the junction structure of the n well 302 or the p substrate 304. In general, the junction breakdown voltage is approximately 8V to 10V for devices fabricated by the 0.25 um technology.